====== Programming - Make - Basic Make Example ====== ===== Basic Example ===== ==== Create a C program ==== #include int main() { printf("Hello World"); return 0; } ---- ==== Create a Makefile ==== hello: hello.c ---- ==== Run Make ==== make returns: cc hello.c -o hello **NOTE:** This compiles the C program. Most distributions will have cc pointing to the default C compiler. ---- ==== Run Make Again ==== make returns: make: 'hello' is up to date. **NOTE:** As nothing has changed, there is no need for Make to recompile the C program. To have the program be recompiled: * Run **touch hello.c**, or * Delete the compiled program, **rm hello**, or * Modify the C program and run make again. ---- ===== Enhanced Make ===== Use variables within the Makefile: CC=gcc CFLAGS=-g hello : hello.c returns: gcc -g hello.c -o hello ---- ===== Add further options to the Makefile ===== CC=gcc CFLAGS=-g # Comment next line to turn off optimization CFLAGS+=-O hello : hello.c **NOTE:** The implicit rule being used is: $(CC) $(CFLAGS) $(CPPFLAGS) hello.c -o hello ---- ===== Use an object ===== Besides compiling, the Makefile can also link the object files: hello : hello.o mylib.o hello.o : hello.c hello.h mylib.h mylib.o : mylib.c mylib.h **NOTE:** Thanks to the default rules, this is all that is needed by Make. The make program is smart enough to see that it needs hello.o, it will go find the rule for hello.o and so on. Of course, additional lines can be added to control further what happens for the build process.